Abstracts:The widespread use of fluorinated gases in semiconductor manufacturing has raised significant environmental concerns due to their high global warming potential (GWP). To address this issue, we developed a systematic methodology for screening and evaluating low-GWP F-gases based on density functional theory (DFT) calculations. The infrared absorption cross-section (ACS) spectra and radiative efficiencies (RE) of candidate gases were predicted and systematically corrected using an empirical scaling factor derived from the correlation between calculated and experimentally measured RE values. This correction significantly improved the accuracy of GWP predictions. The methodology was successfully validated against representative F-gases, yielding GWP1oo estimates that closely align with reported values for high-GWP gases (GWP1oo=2,240), mid-GWP gases (GWP1oo=87), and low-GWP gases (below GWP1oo=10). Notably, several candidate gases, such as COF2, CF3OCFCF2, CF3C(O)CF(CF3)2, and C6F6, exhibited estimated GWP1oo values of 1.79, 2.69, 3.03, and 7.56, respectively, which are consistent with reported values. They were re-confirmed by the proposed method as promising low-GWP alternatives to conventional high-GWP etching and cleaning gases. By adopting a practical, accessible DFT methodology, this approach delivers reliable comparisons of GWP values among candidate gases and supports rapid, on-site GWP assessments without requiring specialized expertise.

Abstracts:This work reports the successful integration and processing of hundreds of GaN on Silicon wafer lots devoted to 100V Monolithic GaN power device within a standard 8-inch silicon fab primarily dedicated to BCD/CMOS technology production. By addressing key challenges related to gallium cross-contamination and equipment compatibility with thicker GaN on Si substrates, a comprehensive contamination management strategy was developed and implemented. This strategy includes dedicated equipment classification, backside wafer protection, optimized cleaning procedures for GaN etching tools, and rigorous monitoring using TXRF measurements. The approach enabled reliable, high-mechanical yield of GaN wafer device fabrication without impacting existing BCD/CMOS production lines, demonstrating the feasibility of coexisting GaN and silicon technologies in a shared manufacturing environment. This achievement paves the way for cost-effective scaling of GaN power device production within mainstream semiconductor fabs.

Abstracts:As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture’s operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS’89 and OpenCores benchmarks compared to prior work.

Abstracts:The speed fluctuations of the magnetically suspended turbo molecular pump (MSTMP) induced by disturbances can lead to particle recoil within the process chamber, thereby contaminating the vacuum environment of the chamber. This paper focuses on the study of disturbance rejection control for the speed of the MSTMP. An adaptive linear extended state observer (ALESO) based on reinforcement learning (RL) is used to observe and compensate for disturbances, thereby improving the performance of the MSTMP. First, a bandwidth-adaptive linear extended state observer is designed to observe the speed and disturbances of the PMSM. Next, to enhance the observer’s performance, a compensation term for the speed observation error is added to the disturbance observation. Additionally, a reinforcement learning algorithm is designed to optimize the coefficients of the bandwidth adaptation law and the observation error compensation term. Simulation and experimental results on an MSTMP prototype validate the effectiveness of the proposed method.

Abstracts:The crystal lifting and rotating mechanism (CLRM) is the key motion device during the growth process of monocrystalline silicon. The operation state of CLRM has a direct influence on the quality of the monocrystalline silicon. Typically, the CLRM operates at a slow speed with subtle changes in state and inconspicuous signal features, which makes it hard to effective diagnosis the working condition. In this article, a vibration-signal-based diagnosis method is proposed to monitor the operation status of the CLRM. Firstly, the vibration signals are collected by the sensor installed on the certain location of the CLRM. A signal expansion strategy is then designed to extent the original signal by integration of variational mode decomposition and canonical polyadic decomposition. The characteristic of the signal is enriched. After that, the features of the expanded signals are extracted using permutation entropy, followed by the K-nearest neighbor classification. Three representative experiments are conducted to verify the performance of the proposed method using different datasets, including the benchmark vibration signal dataset, signals acquired from the experimental platform established by our laboratory, and the signals acquired during the actual growth process of monocrystalline silicon.

Abstracts:The industry’s first, and arguably still the fastest, automated integrated circuit fabricator was operational at IBM in East Fishkill, NY, in 1974. It demonstrates the highest possible level of automated sequential process integration in a wafer fab. It took less than one day to create IBM RAM-II chip circuits on blank wafers. The fast turnaround time was achieved with a system architecture that is unique even today. All operations required to process a wafer between one photoresist pattern exposure and the next were integrated into a single automobile-sized automated machine called a “sector”. The fabricator consisted of a pattern exposure station, five automated wafer processing sectors, a monorail single-wafer “taxi” connecting them, and a computer-based production control and monitoring system. This paper describes the processing equipment and achievements of this little-known pioneering demonstration of wafer processing automation. It was initiated and managed by William E. Harding to demonstrate the practicality and advantages of full automation, single-wafer processing, fast turn-around time and continuous operation for integrated circuit manufacturing. Harding’s groundbreaking automated wafer processor produced RAM-II circuits at a good yield in 20 hours turnaround time, averaging 5 hours per layer.

Abstracts:In semiconductor manufacturing, a multifunctional process module (MPM) can perform multiple processing steps by adjusting its functional settings. This enhances the reconfigurability of cluster tools and allows them to flexibly adapt to diverse production requirements. However, the different function settings of the MPM change the number of processing modules and generate multiple alternative processing routes. Deadlocks occur more frequently in wafer manufacturing processes with flexible routes. The flexible configuration of MPM function leads to a highly complex and large-scale model. Proper configuration of MPM can optimize lot scheduling and improve processing efficiency. Thus, based on the functional setting of MPM, process-oriented Petri nets (POPNs) are established to describe the transient and steady state processing of the system, and control explanations are developed to avoid the system deadlock. Then, based on the evolving mechanism of the Petri nets, the temporal properties of the system under the earliest starting strategy (ESS) are analyzed. An algorithm based on ESS is developed to compute the makespan of wafers in a lot and optimize the settings of the MPM function. Experimental results demonstrate that for scheduling problems unsolvable by the mixed-integer programming (MIP) model, the algorithm can adaptively minimize system lot completion time by reasonably setting the function of MPM.

Abstracts:Studies have shown that when the door of a Front Opening Unified Pod (FOUP) opens, the moisture or airborne molecular contamination (AMC) in the microenvironment can be influenced by the equipment layout, forming a skewed flow field. This skewed flow field can allow contaminants to enter the FOUP, adversely affecting the yield of the semiconductor manufacturing process. To effectively eliminate contaminants inside the FOUP, in addition to the common method of purging the FOUP, a laminar air curtain (LAC) device can be added to the FOUP door. This device introduces compressed dry air (CDA) at the interface between the microenvironment and the FOUP, forming flow barrier. This method effectively controls the cleanliness and humidity inside the FOUP. Currently, with the use of the laminar air curtain device, the humidity inside the FOUP significantly decreases. However, when the air reaches the bottom of the wafer box, it tends to diffuse outward, allowing contaminants to invade. To enhance the barrier effect of the air curtain, increasing the flow rate of the injected air is considered, but this can cause deformation of the perforated plate. Since the laminar air curtain device is installed near the door of the Load-Port Unit (LPU), the deformed perforated plate might collide with the LPU door, causing structural damage, generating particles, or displacing the laminar air curtain device, thus compromising its ability to effectively block contaminants from entering the FOUP. The previously developed filter-type laminar air curtain device has met the high flow rate (700 L/min) requirements and improved issues related to deformation and particle generation caused by high flow rates. However, comparative testing of performance across multiple samples in mass production is lacking. Therefore, this study will optimize the configuration of the filter-type laminar air curtain device, including the use of a perforated plate at the outlet and an airflow diffusion device inside the structure. After mass production, we will conduct performance comparisons, including indicators such as airflow uniformity and particle concentration. We expect that advancements in this research and technology will promote broader application of the filter-type air curtain device in the semiconductor industry.

Abstracts:Accurate endpoint detection is critical in semiconductor plasma etching. Optical emission spectroscopy data contains information about the endpoint, but its analysis requires significant domain knowledge, and it contains large noise when the open area ratio is small. This paper proposes an interpretable data-driven endpoint detection method for small open area etching, leveraging transfer learning. First, we propose a formal metric quantifying the significance of endpoint trend in each wavelength signal and select the wavelength signals that are most sensitive to endpoint variations. Second, we devise an asymmetric autoencoder to uncover the endpoint trend in the noisy signals. Its asymmetric architecture incorporates nonlinear characteristics while ensuring the latent feature reflects the endpoint trends of the individual signals. Experimental results show that the model that learned the large open area etching (11.1%) can detect the endpoints of the small open area etching (0.5%) with the relative mean absolute error less than 0.6%, and amplify the signal-to-noise ratio by a factor of 2-3. Furthermore, the analysis of the selected wavelengths provides deeper insights into the underlying physical processes. The proposed method can be applied with minimal domain knowledge, while its results allow for exploring physical interpretations.

Abstracts:The defect of the lighting-emitting diode (LED) chip is inevitable in the manufacturing process, which makes it necessary to classify the defective LED-chips with a robust inspection system to guarantee high production efficiency. Recently, convolutional neural networks (CNN) have attracted considerable attention in defect classification. With the miniaturization of chip size, it is difficult to recognize the defective chip using the traditional deep CNN, which obtains the large receptive field of the last layer so that the spatial details are ignored and small defects cannot be detected. To address this issue, we propose a multi-scale content-aware enhancement dual-branch CNN for LED-chip defect classification, which is a shallow network with a strong cross-layer feature extraction ability. Aiming at recognizing different sizes of the defect and filtering the noise, a multi-scale content-aware enhancement module is proposed to highlight the important features and inhibit the noise with three different receptive fields, which is beneficial for the detailed and semantic information extraction. Furthermore, a joint loss is adopted to improve the classification ability and facilitate the recognition of difficult samples. Experiments show that the proposed model achieves high recognition accuracy of 95.258% with a low model complexity, which is superior to state-of-the-art methods.