Abstracts:A non-contact power transfer mechanism via an ionic liquid (IL) to a bipolar electrostatic wafer chuck (ESC) was developed. The liquid power transfer method can supply voltage to the ESC set on a floating bearing, with no metal contact points and friction contamination. It intended for use in vacuum processes for semiconductor fabrication. In this transfer mechanism, electrostatic charge-up occurs in the IL which is concerned with the degradation of the IL. Thus, a non-oxidized metal nanoparticle-dispersed IL was prepared to reduce the charge-up, and its effect on charge reduction was investigated. The nanoparticle-dispersed IL exhibited a significant reduction in charge-up compared to the pure IL during voltage supply to the ESC. Although decomposition products obtained from the sputtering process were detected from the sputtered IL in a vacuum environment, the partial pressure values of these products were set to 10-9 Pa, indicating that the damage to the IL from sputtering was limited. The non-oxidizing metal nanoparticle-dispersed IL effectively prevented IL degradation and was useful for the non-contact power supply mechanism. It exhibits the potential to contribute to advancements in semiconductor manufacturing equipment.

Abstracts:Accurate and efficient detection of internal defects in chips is crucial for ensuring the reliability and yield of electronic products. However, conventional object detection models often struggle to identify such defects in ultrasonic images due to their extremely small size and low contrast. To overcome these challenges, a novel detection framework that combines image processing with a Transformer-based Attention Feature Fusion YOLO model (TAFF-YOLO) is proposed in this paper. The framework first employs image processing methods to extract individual chip images and then applies a handcrafted feature generation algorithm for data augmentation to mitigate overfitting. Subsequently, the TAFF-YOLO model is introduced for precise defect localization. Specifically, a Deformable Attention Background Suppression Module (DABSM) is integrated to enhance global contextual information and the receptive field for detecting small objects. Additionally, the feature fusion network (neck) is augmented with a ResBlock and Convolutional Block Attention Module (ResCBAM) to focus the model effectively on critical defect regions while suppressing irrelevant background noise. A Smooth Intersection over Union (SIoU) loss function further stabilizes the training and enhances localization accuracy. Experimental results from two private datasets and one public dataset demonstrate that the proposed method achieves an average precision of 90.9%, with a compact model size of 2.6 million parameters and an inference speed of 167.3 FPS, effectively balancing detection accuracy, model complexity, and processing speed. This indicates significant promise for real-time industrial chip inspection applications.

Abstracts:Critical patterns are layout patterns that cannot be corrected by standard MB-OPC with enough accuracy. Since they are infrequent, lithography applications targeting critical patterns such as inverse lithography technology (ILT) can suffer from insufficient samples. We propose a method to synthesize critical patterns and their mask patterns. (1) A multilayer perceptron (MLP) model is constructed to predict the probability that the feature vector of a mask pattern, obtained through a mask encoder, is critical. A key is to perform gradient ascent through the MLP network, which has been trained before, to identify some new critical feature vectors. (2) Such vectors are decoded, using a mask decoder, into an image which is refined using a conditional generative adversarial network (cGAN) for final critical mask patterns. (3) A U-Net model is applied to critical mask patterns to discover the critical layout patterns.Experiments are performed for quick ILT through U-Net model. When the synthesized critical mask- and layout-patterns are used to train the U-Net, ILT becomes more accurate and the standard deviation of EPE distribution for ILT outputs is reduced by 36.3%. Lithography modeling is considered for another application of the proposed method. The RMSE of lithography model is reduced by 30.7% when the model is calibrated with synthesized critical layout patterns, compared to base model built with standard test patterns.

Abstracts:This paper presents a novel on-wafer self-powered wireless sensing module for extreme ultraviolet (EUV) lithography, advancing prior designs through the integration of a Gate Voltage Controlled Oscillator (GVCO) and an optimized ultra-thick metal on-chip antenna (OCA) for enhanced stability and transmission properties. The surface sensing pad captures incident photons, inducing energy via a coupling device to control the GVCO, whose output frequency reflects real-time EUV intensity. The output frequency signal can be wirelessly transmitted to the receiver through an OCA. It enables real-time monitoring of on-wafer EUV exposure parameters in advanced lithography systems without an external power source, thereby facilitating the yield control of advanced CMOS processes.

Abstracts:Electromigration, driven by increasing current densities in scaled integrated circuits, poses a serious reliability challenge in semiconductor manufacturing, often culminating in void formation and interconnect failure. As interconnect dimensions shrink to the nanoscale, the influence of microstructural features and grain morphology on interconnect reliability and degradation mechanisms becomes increasingly significant. In this work, we develop a physics-based phase field model to investigate the void formation and evolution in copper interconnects subjected to electromigration. Our simulations closely align with experimental trends, revealing that voids predominantly emerge at or initiate from the cathode end, with their evolution strongly influenced by grain morphology. In the surface diffusion-limited scenario (SDLS), grain boundaries significantly promote void formation, resulting in increased void sizes. Under the grain boundary diffusion-limited scenario (GBDLS), void nucleation in bamboo structure (BS) and polycrystalline structure (PS) interconnects occurs relatively early, often initiating near the interface between the copper and the capping layer. The voltage distribution exhibits noticeable inhomogeneity, with high electric field intensities localized at grain boundaries and void surfaces. The electromigration-induced mass flux predominantly flows from the bottom right toward the left. Additionally, an increased number of copper grains leads to larger voids, with a more pronounced effect in the SDLS. Furthermore, electromigration-induced void growth progressively reduces electrical conductivity. These findings elucidate the complex interplay between grain morphology, electromigration-driven void formation, and electrical performance degradation in copper interconnects, and are anticipated to offer valuable insights into microstructure-dependent failure mechanisms while supporting process optimization in advanced interconnect fabrication.

Abstracts:The convolutional neural network (CNN) based model has been widely used for wafer map defect pattern recognition. However, it often fails to detect patterns effectively after a few months of deployment due to shifts in data distribution, usually linked to aging inspection tools or recipe changes. To address this issue, researchers have turned to transfer learning techniques. However, most methods require labeled data for the target dataset, which is time-consuming and labor-intensive. Unsupervised domain adaptation (UDA), a transfer learning technique, requires no human labeling and performs better than conventional methods. This study introduces deformable convolutional encoder adversarial discriminator domain adaptation (DC-ADDA), which adapts the deformable convolutional network (DC-Net) as an encoder in the adversarial discriminative domain adaptation method. Using MixedWM38 and synthesized multi-bin wafer bin maps (SWBMs) as source datasets with WM-811K as the target, DC-ADDA outperforms other methods across transfer learning, encoders, and domain adaptation scenarios. The proposed DC-ADDA method achieves an accuracy of 66.46%, a precision of 68.13%, a recall of 69.63%, and an F1-score of 68.41% when applied from MixedWM38 to WM-811K. When applied from SWBMs to WM-811K, it achieves an accuracy of 75.61%, a precision of 75.20%, a recall of 74.81%, and an F1-score of 74.81%.

Abstracts:During reflow soldering, Metal-Oxide- Semiconductor Field-Effect Transistors (MOSFETs) are prone to internal voids. A high void ratio for a MOSFET significantly affects its electrical performance to further decrease the reliability and lifespan of the electronic device. In this article, a multi-scale adaptive inspection framework is proposed to inspect internal voids in MOSFETs through X-ray imaging. First, a location-aware vertex detection scheme is utilized to detect the transistor region possibly involving the voids, which makes full advantages of the neighborhood grayscale distributions of the transistor region vertices. Then, after the detected transistor region is preprocessed and divided into several patches, coarse-to-fine void inspection is performed on the patches for void inspection. Specifically, a multi-scale scheme is proposed for coarse void inspection to identify whether the patches involve the potential voids, in which an identification function is defined by integrating the constructed multi-scale radial decaying weight matrix and a fitting metric to characterize the patches. An adaptive thresholding scheme is proposed to finely inspect the voids in the MOSFETs, in which the segmentation threshold model is constructed based on grayscale distributions of the MOSFET X-ray images. Finally, the void ratio is calculated according to the detected transistor and the voids. Experimental results indicate that the proposed framework achieves better inspection performance for voids in MOSFETs than some existing methods at the speed of 0.812s per MOSFET, with an average Dice of 0.8852, an Accuracy of 97.11%, and an F1-score of 0.9819.

Abstracts:In semiconductor manufacturing, achieving precise overlay alignment between successive lithography layers is critical. Current methods face challenges due to non-lithographic process-induced wafer shape changes that cause in-plane distortions (IPD). This study presents Wave Front Phase Imaging (WFPI), a new technique that measures wafer shape by analyzing the intensity of reflected light without requiring interference. WFPI’s capability to produce high-resolution shape maps allows for accurate prediction of IPD. WFPI utilizes two intensity images at distinct optical distances to construct phase maps indicative of wafer topography. Our evaluation on test wafers reveals that WFPI can accurately predict IPD, matching lithography scanner outputs. The paper also shows that WFPI can acquire the wafer shape on a fully patterned 300mm silicon wafer on both frontside and backside. This technique shows the potential to significantly improve overlay accuracy, supporting advanced semiconductor manufacturing processes.

Abstracts:Fan-out packaging (FOP) is promising for Mini/Micro-LED manufacturing, while chip misalignment occurs during the transferring process owing to the insufficient placement accuracy and the mismatched thermal expansion of packaging materials. This position deviation leads to interconnect misalignment between the redistribution layer (RDL) and chip electrodes, ultimately reducing packaging yield. This paper proposes a laser direct writing lithography (LDWL)-enabled FOP method to self-adapt the LED chip position deviation. The LDWL pattern is generated by machine vision according to the actual chip positions, ensuring precise interconnection between the RDL and chip electrodes. The proposed method has been successfully used to manufacture FOP LED devices, preserving excellent optoelectronic and mechanical performances, with the chip deflection tolerance of ±10° and the line width of approximately $25~\mu $ m. Our LDWL-FOP method can effectively compensate for the chip misalignment during the packaging process, showing great potential for the high-yield manufacturing of Mini/Micro-LED chips.

Abstracts:As semiconductor integrated circuits become increasingly miniaturized, overlay metrology has garnered significant attention. Moiré marks offer superior accuracy and robustness compared to conventional grating marks; however, their sensitivity to various optical system parameters can affect measurement precision. This study presents a novel quality index, termed the signal shape index, to quantitatively assess the quality of Moiré marks, which are a crucial factor in enhancing the reliability of overlay metrology. Current quality indices primarily focus on signal strength, consistency, and asymmetry; however, they inadequately capture vital information regarding the shape of Moiré patterns. To address this limitation, the comprehensive index quantifies the shape of Moiré patterns, providing a more effective evaluation of their quality. This shape-based quality index is compared with the established modulation transfer function index. The new index more accurately reflects the characteristics of Moiré patterns, thereby facilitating the optimization of optical system parameters. Implementing this novel quality index is expected to significantly improve the accuracy of Moiré mark-based overlay metrology, contributing to the stabilization and efficiency of semiconductor manufacturing processes.