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IEEE Design & Test

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This Stuff Is Great—Am I Right?

Scott Davidson

Erratum to “Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence”

Sudeep PasrichaMarilyn Wolf

Keywords:ComputersEthicsArtificial intelligence

Abstracts:Presents corrections to the paper, Erratum to “Ethical Design of Computers: From Semiconductors to IoT and Artificial Intelligence”.

Recap of the 29th ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED’24)

Pascal MeinerzhagenKapil DevJerald Yoo

Keywords:International SymposiumLow-power DesignLow-power ElectronicsPaper SubmissionOrganizing Committee

Abstracts:The ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) was brought back to the United States for the 2024 edition, after a successful 2023 edition in Vienna, Austria. The ISLPED’24 symposium was held on 5–7 August 2024, as an in-person event in the luxurious Hyatt Regency Newport Beach Hotel in the beautiful city of Newport Beach in Southern California. Two large conference rooms and several outdoor areas on the premises of the hotel were reserved for the symposium, providing ample space for presentations and networking among attendees.

Report on the 2024 Embedded Systems Week (ESWEEK)

Alain GiraultTei-Wei KuoFrank Mueller

Keywords:SymposiumEducation ClassesRegular SessionsSpecial SessionRound Of ReviewsComputational InfrastructurePaper SubmissionPoster SessionPaper AwardCyber-physical Systems

Abstracts:Embedded Systems Week (ESWEEK) is the premier event covering all aspects of embedded systems and software. The event brings together three leading conferences (CASES, CODES+ISSS, and EMSOFT), one symposium, five hot-topic workshops, five special sessions, two panels, ten tutorials, seven education classes, two competitions with demos, one PhD forum, and a recruiting event. ESWEEK presents attendees with a wide range of choices unveiling state-of-the-art embedded systems design and hardware/software architectures. Besides, ESWEEK 2024 had a special panel to celebrate 20 years of ESWEEK.

Background Receiver IQ Imbalance Correction for In-Field Testing

Muslum Emir AvciSule Ozev

Keywords:ReceiversTransceiversHardwareDetectorsRadio frequencyRadio transmittersPower measurementCommunication systemsTestingImbalance CorrectionLow-passTest SystemPhase ShiftMatrix MultiplicationCarrier FrequencyDetection PowerDirect ConversionLow OverheadTight IntegrityProcessing NodesAttenuation LevelEllipse FittingLocal Oscillator SignalLow Computational OverheadPhase ImbalanceRF SystemDegrees Of FreedomMonte Carlo SimulationDynamic RangeEffect Of ImbalanceHardware ExperimentsAverage Absolute ErrorCoefficient MatrixEigenvectorsEquality ConstraintsLagrange MultiplierDesign MatrixError FunctionRF BISTIQ ImbalanceDirect-conversion receiversdemodulationcommunication systems

Abstracts:Editor’s notes: Direct-conversion receivers are used in integrated receivers and communication systems. This article proposes a methodology to measure IQ imbalance in direct-conversion receivers. —Partha Pratim Pande, Washington State University, USA

STAR: A Mixed Analog Stochastic In-DRAM Convolutional Neural Network Accelerator

Salma AfifiIshan ThakkarSudeep Pasricha

Keywords:Random access memoryCircuitsCapacitorsComputer architectureLogic gatesStochastic processesDRAM chipsConvolutional neural networksOptimization methodsMachine learningEnergy efficiencyConvolutional Neural NetworkLoad DataStochastic ApproximationHardware AcceleratorsAnalog ComputingReal-valuedConvolutional Neural Network ModelLookup TableCalculation ErrorPower EfficiencyVoltage LevelsConvolutional Neural Network LayersData ConversionArea OverheadFootprint AreaSign Bitstochastic computingin-DRAM processingconvolution neural networks

Abstracts:Editor’s notes: This article addresses the optimization of data movement in accelerating machine learning workloads, one of the most critical issues of state-ofthe- art computing platforms. It presents a novel in-DRAM accelerator for convolutional neural networks using mixed analog-stochastic optimizations and shows significant energy-efficiency improvements. —Umit Ogras, University of Wisconsin, USA

Exploring Resilience of LPDRAM Against RowHammer

Anandpreet KaurPravin SrivastavBibhas Ghoshal

Keywords:Random access memoryMemory modulesProgram processorsProbabilistic logicObject recognitionHardwareResiliencePerformance evaluationParametric studyEmbedded systemsCyberattackDRAM chipsDeterministicLack Of EvidenceRepeat TestingComputing DevicesAdversarial AttacksCircuit LevelMemory ModuleARM ProcessorConfiguration ParametersMap InformationLog FilesSusceptibility RegionsData CachePhysical RegionMemory RegionsLPDRAMRowHammerHardware attacks and countermeasuresEmbedded devicesSecurity

Abstracts:Editor’s notes: This article investigates, for the first time, how RowHammer attacks impact LPDRAM memories. The findings reveal that RowHammer causes bit flips at specific memory locations, which facilitates more predictable attacks.—Kanad Basu, University of Texas at Dallas, USA

Silicon Lifecycle Management (SLM): Requirements, Trends, and Opportunities

Mehdi TahooriSeyedeh Maryam GhasemiYervant Zorian

Keywords:ReliabilityMonitoringComplexity theoryTemperature sensorsSiliconPerformance evaluationManufacturingLife cycle assessmentIntegrated circuitsSystem-on-chipSiliconLifecycle ManagementInfrastructureTechnological AdvancesComplex SystemsSystem PerformanceTest PhaseSystem ReliabilityHealth MonitoringHigh-performance ComputingFault-tolerantDesign PhaseQuality TestingCommunication ProtocolEntire Life CycleMonitoring Of ParametersSemiconductor IndustrySecurity ProtocolsFailure AnalysisHardware ComponentsSemiconductor DevicesCybersecurityTime-to-digital ConverterTelemetry DataProper ActivityHot ElectronsElectromigrationProduct Lifecycle ManagementSensor DataSilicon Lifecycle Managementin-situ monitoringchip health monitoring

Abstracts:Editor’s notes: Silicon lifecycle management (SLM) is an integrated approach that encompasses the entire lifecycle of silicon-based hardware components, with a primary focus on integrated circuits and complex systems on chips. This article presents a thorough survey regarding various challenges associated with SLM. —Partha Pratim Pande, Washington State University

Still Making Noise: Improving Deep- Learning-Based Side- Channel Analysis

Jaehun KimStjepan PicekAnnelie HeuserShivam BhasinAlan Hanjalic

Keywords:TrainingTuningOverfittingSide-channel attacksMachine learning algorithmsMeasurementLinear programmingEntropyDeep learningSystematicsNeural NetworkMachine LearningDeep LearningOverfittingLearning AlgorithmsDeep Neural NetworkHyperparameter TuningFeature EngineeringSide-channelDirect AttackTarget CaseSecret InformationNumber Of TracesTraining SetConvolutional Neural NetworkValidation SetGaussian NoiseRecent ResultsData AugmentationMultilayer PerceptronRegularization TechniquesBatch NormalizationCommon ExamplesEarly Stopping

Abstracts:Editor’s notes: Side-channel attacks have been undermining cryptosystems for almost three decades. Advances in machine learning techniques have shown great promise in improving the performance and efficiency of side-channel attacks, even on systems with countermeasures. This article provides a systematic approach to applying ML techniques for side-channel attacks. —Jeyavijayan Rajendran, Texas A&M University, USA

Remote Power Side- Channel Attacks on FPGAs

Mark ZhaoG. Edward Suh

Keywords:Field programmable gate arraysLogicCircuitsMonitoringPower demandLogic gatesSwitchesChannel modelsSide-channel attacksChannel AttacksRemote PowerRemote SideData CenterPower ConsumptionVoltage DropPhysical AccessSecurity VulnerabilitiesSide-channelEnergy MeterDynamic Power ConsumptionOscillation FrequencyInverterLookup TableVoltage RegulationCircuit ActivitySecret KeyElectrical NoiseActive SwitchesLeast Significant BitPower Distribution NetworkSum Of Consumptionfield programmable gate arrayring oscillatorpower analysis attackside-channel attacksystem-on-chip

Abstracts:Editor’s notes: Side-channel attacks, like those exploiting power and timing, are generally thought to require physical access to a system. This research challenges that idea by demonstrating how such attacks can be carried out on remote systems without physical access. It emphasizes the need to rethink how modern shared-FPGA systems are designed, prioritizing security as a core consideration. –Jeyavijayan Rajendran, Texas AM University, USA

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