Abstracts:As supply voltages continue to decrease, it becomes harder to ensure that the voltage drop across a diode connected BJT is sufficient enough to conduct current without sacrificing die area. One such solution to this potential problem is the diode connected FinFET operating in weak inversion. In addition to conducting appreciable current at voltages significantly lower than the power supply, the diode connected FinFET reduces the total area for the bandgap implementation. A 14 nm bandgap reference was created and simulated across Monte Carlo for 100 runs at nominal supply voltage and 10% variation of the power supply in either direction. The average temperature coefficient was measured to be 153.6 $\frac{ppm}{{}^{°}\mathrm{C}}$ and the voltage adjustment range was found to be 204.1 mV. The two FinFET subthreshold diodes consume approximately 2.8% of the area of the BJT diode equivalent. Utilizing an appropriate process control technique, subthreshold bandgap references have the potential to overtake traditional BJT based bandgap architectures in low power, limited area applications.

Abstracts:A significant increase in the accuracy of a conventional bipolar monolithic radio-frequency bipolar peak detector is robustly achieved over a wide amplitude range using a simple nonlinear loading circuit. The loading circuit provides two voltage-controlled auxiliary currents which cancel the errors by altering the original DC currents flowing through the core transistors, according to the level of the detected voltage. Expressions are derived for the auxiliary currents for perfect error cancellation; a good approximation is provided by a simple cross-coupled transistor pair, but more complex circuit structures can be employed for enhanced range and/or robustness. Because the loading circuit operates essentially at DC, the high-frequency nature of the original peak detector is preserved. The presented concept and its various circuit implementations are discussed and validated in simulation, and are expected to work in a large variety of modern bipolar or BiCMOS integrated-circuit technologies, where parasitics-free, simple exponential-law models accurately represent the operation of the transistors up to very high frequencies.

Abstracts:We investigated the impact of etch angles on cell characteristics of 3D NAND flash memory structures. The cell characteristics were extracted from simulations with an empirical etch profile, which was analyzed through comparisons to completely vertical conditions. Here, we observed that a narrowing of the poly-silicon channel width due to etch angles increased the channel resistance, which resulted in an on-current degradation of approximately 19% for an etch angle of 89.2°. The degradation in cell characteristics also became worse as the number of word-lines changed from low to high levels. Additionally, the difference in channel hole size between upper and lower stage aggravated the cell uniformity along the channel, hence the threshold voltage distribution was broadening in the smaller etch angle.