An automatic mode low-jitter pulsewidth control loop (PWCL) with enhanced operation frequency is presented in this paper. Using the automatic mode selector (AMS), the proposed PWCL can operate between pulsewidth modulating mode and tracking mode adaptively, avoiding extra power dissipation when a 50% duty cycle input clock is added. Based on the analysis of the delay time between the fixed falling edge and the rising edge generated by PWCL cycle, an auto delay time adjusting delay stage (ADTDS) is proposed to expand the locking frequency range of PWCL. Moreover, an improved charge pump and a novel delay stage are utilized to decrease the supply-induced jitter. The experimental results demonstrate that the proposed PWCL can lock the clock duty cycles for no more than 50±1% with 10–90% input duty cycle from 5MHz to 750MHz. At pulsewidth modulating mode, the measurement power dissipation and peak-to-peak jitter are 9.52mW and 7.72ps (rising edge) and 9.45ps (falling edge), respectively, while at tracking mode, 0.6mW and 10.1ps achieved with an operating frequency of 750MHz. The core area of chip is 220µm×310µm².

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measurement power dissipation supplyinduced charge pump auto delay time adjusting delay stage adtds operation locking frequency pwcl automatic mode selector ams duty cycle input clock falling edge automatic mode lowjitter pulsewidth control loop pwcl peaktopeak jitter

Shubin Liu, Zhangming Zhu, Wei Guo,.An automatic mode low-jitter pulsewidth control loop with broadband operation frequency. 58 (0),14-22.

Shubin Liu, Zhangming Zhu, Wei Guo,"An automatic mode low-jitter pulsewidth control loop with broadband operation frequency" 58

Shubin Liu, Zhangming Zhu, Wei Guo,"An automatic mode low-jitter pulsewidth control loop with broadband operation frequency"