Bias-Temperature Instability (BTI) is one of the key device reliability concerns for both digital and analog circuit operations. Features of work-function metal (WFM) for VT modulation in 10nm FinFET process technology results in WFM dependent BTI characteristics. Similar levels of aging degradation to those of previous 14nm technology were observed in both DC and AC operations. As BTI-induced VT variability is expected to increase with 3D fin dimension scaling, such variability must be accurately characterized and considered for circuit designs. This paper reports the impact of transistor- level BTI degradation on circuits by studying Ring Oscillator (RO) and SRAM. The SRAM cell stabilities in terms of SNM (Static Noise Margin) and WRM (Write Margin) were further studied through SRAM HTOL stresses by characterizing Vmin shift. Robust 10nm SRAM and product level HTOL reliability up to 500h were demonstrated.

+More

product level htol reliability ring oscillator ro snm static noise margin instability btiinduced vinf locposttinf variability aging sp025nm workfunction metal wfm device reliability circuits transistor level bti degradation wrm write margin vinf locpostmininf shift robust 10hsp circuit designs 3d fin dimension wfm dependent bti characteristics sram htol stresses digital and analog circuit

Sangwoo Pae, Gunrae Kim,Minjung Jin, Kangjung Kim, Hyewon Shim, Jinju Kim, Yoohwan Kim,.Investigation of BTI characteristics and its behavior on 10nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack. 81 (0),.

Sangwoo Pae, et al."Investigation of BTI characteristics and its behavior on 10nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack" 81

Sangwoo Pae, Gunrae Kim,Minjung Jin, Kangjung Kim, Hyewon Shim, Jinju Kim, Yoohwan Kim,"Investigation of BTI characteristics and its behavior on 10nm SRAM with high-k/metal gate FinFET technology having multi-VT gate stack"