This brief describes the design and implementation of a 250-Mb/s to 6-Gb/s single-loop referenceless clock and data recovery circuit. The clock frequency multiplier and the referenceless frequency acquisition circuit are used to cover a wide-range data rate. The clock frequency multiplier is proposed to generate the 6-GHz clock with low jitter. In addition, the voltage-controlled oscillator operates at 1/5-rate frequency of the sampling clock, which has a merit of low power consumption. The proposed circuit achieves 9.56-ps rms jitter, consumes 13.2 mW at 6 Gb/s, and occupies 0.0944 mm² in a 65-nm CMOS technology.

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voltagecontrolled oscillator rms widerange data clock frequency multiplier jitter 250mbs to 6gbs singleloop referenceless clock and data recovery referenceless frequency acquisition circuit

Ja-Young Kim, Sang-Geun Bae, Chulwoo Kim, Junyoung Song, Jungtaek You, Sewook Hwang,.A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier. 64 (6),650-654.

Ja-Young Kim, et al."A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier" 64

Ja-Young Kim, Sang-Geun Bae, Chulwoo Kim, Junyoung Song, Jungtaek You, Sewook Hwang,"A 250-Mb/s to 6-Gb/s Referenceless Clock and Data Recovery Circuit With Clock Frequency Multiplier"