Abstracts:RF to dc passive rectifiers can benefit from the superior performance at low voltage of tunnel transistors. They have shown higher power conversion efficiency (PCE) at low input power than Si FinFETs counterparts. In this paper, we analyze the limitations of typical tunnel field-effect transistor rectifier topologies associated with the forward biasing of their intrinsic diode and show that this can occur at relatively weak input signals depending on the specific characteristic of the used tunnel device. We propose a simple modification in the implementation of the rectifiers to overcome this problem. The impact of our proposal is evaluated on the widely used gate cross-coupled topology. The proposed designs exhibit similar peak PCE and sensitivity but significantly improve PCE for larger input signal amplitude and larger input power.

Abstracts:Given that power consumption and short-channel effects exist in a trade-off relationship, there has been much effort to investigate short-channel transistors which enable relative reductions in the operating voltage. Recently, the feasibility of transistors operating at ultra-low voltages with a nanometer-scale channel length has been extensively investigated for future nanoelectronics. Here, we demonstrate solution-processed single-walled carbon nanotubes-based thin-film transistors (SWCNT-TFTs) with a sub-20-nm-channel operating at ultra-low voltages which utilize an electromigration technique that induces a broken bridge of nanoparticles. By employing the post-treatment process of thermal annealing in a vacuum, the charge transport of the short-channel SWCNT-TFTs was improved. The origin of such improvements is presumed to reduce the charge impurities, including organic/inorganic residues as defect states, as well as to improve electric contact between the SWCNT and the metal electrode, which strongly affects the one-dimensional charge transport.

Abstracts:AlN Schottky diodes with various device geometries were fabricated on sapphire substrate and their temperature-dependent current–voltage characteristics were analyzed. At forward bias, high ideality factors were obtained, indicating a large deviation from the ideal thermionic emission model. At reverse bias, the breakdown voltage showed a negative temperature dependence, and the leakage current was well described using a 2-D variable-range hopping conduction model. Furthermore, the breakdown voltages and leakage currents of the devices showed a strong dependence on the surface distance between the ohmic and Schottky contacts, but a relatively small dependence on the area of the Schottky contacts. These results suggest surface states between ohmic and Schottky contacts play a more important role than the metal/AlN interface in determining the reverse breakdown and leakage current of AlN Schottky diodes. A quantitative study of AlN Schottky diodes at high temperature reveals a geometry-dependent surface breakdown electric field and surface leakage current. Surface passivation and treatments may enhance the device performances and impact the reverse breakdown and current leakage mechanisms. These results will serve as the guidance for the design and fabrication of future AlN electronic devices.

Abstracts:This paper presents the design and characterization of high conversion-gain pixels in a 180-nm CMOS image sensor process. By reducing overlapping capacitance between a floating diffusion and transfer gate, output-referred pixel conversion gain as high as 118uV/e- and read noise as low as 1.8e- rms are experimentally achieved without significant lag. A dark current of 38 pA/cm² is measured at 60 °C. Comparison between the proposed devices and a baseline pixel regarding device structure and characterization results is also presented.

Abstracts:Thin film transistors (TFTs) with amorphous InMgO (a-IMO) and InGaZnO (a-IGZO) stacked active layers are proposed to implement high-performance ultraviolet (UV) detectors. In this structure, the IGZO layer serves as the conductive layer and the IMO layer acts as the light absorption layer. The fabricated a-IGZO/a-IMO TFT shows comparable electrical characteristics to those of the conventional a-IGZO TFT as well as high UV photocurrent gain with good visible-blindness. In addition, the a-IGZO/a-IMO TFT-based sensor operates with stable and successive light detection. Thus, the a-IGZO/a-IMO TFT has been demonstrated to be able to act as both sensing and switching devices in the pixels of UV image sensors.

Abstracts:In this paper, for the first time, the performance analysis of short channel In_0.53Ga_0.47As quantum well (QW) 3-D tri-gate technology with advanced high- $kappa $ gate dielectric, TaSiO_x is presented. We benchmark the projected performance of sub-10 nm In_0.53Ga_0.47As transistor technology as a function of fin width, fin aspect ratio, and gate length scaling based on present-day lithographic advancement aiding InGaAs QW tri-gate technology as a replacement to Si for sub-10 nm transistor technology. The highly scaled oxide (EOT ~ 12 $mathring {text{A}}$ ) while retaining superior interfacial properties ( $text{D}_{mathrm{ it}}~sim ~4times 10^{11}$ cm⁻²eV⁻¹) provides higher ON current for given idle performance. Furthermore, the simulated In_0.53Ga_0.47As tri-gate transistor exhibits superior gate electrostatic control with low OFF-state current ( $text{I}_{mathrm{ OFF}}$ ) ~ 24.5 nA/ $mu text{m}$ , peak transconductance ( $g_{m}$ ) ~ 2 mS/ $mu text{m}$ and high ${I} _{mathrm{ ON}}/{I} _{mathrm{ OFF}}$ ratio $sim ~2.3times 10^{3}$ , aiding the case of alternate channel transistors for high-speed and low-power CMOS logic.

Abstracts:The on-resistance (R_ON) degradation in normally-OFF GaN high electron mobility transistors has been evaluated both experimentally and by means of numerical simulations by analyzing its drift during device pulse-mode operation. Experimental data showed that the device R_ON measured during the on-time interval of the switching period increased with time resulting in a thermally activated process with an activation energy ${E}_{A}=0.83$ eV. For the first time, numerical simulations have been carried out in order to evaluate the device R_ON drift during pulse-mode operation and to understand the physical phenomena involved. A good qualitative agreement between experimental and simulated data has been obtained when considering in the simulated device simply a hole trap located at 0.83 eV from the GaN valence-band, an energy level which has been linked in previous works to carbon-doping within the GaN buffer.

Abstracts:The rapid development of RF power electronics requires amplifier operating at high frequency with high output power. GaN-based HEMTs as RF devices have made continuous progress in the last two decades showing great potential for working up to G band range. However, vertical structure is preferred to obtain higher output power. In this paper, we have designed and fabricated GaN static induction transistor using the self-aligned technology, which was accomplished mainly by using a SiO₂ lift-off step in buffered oxide etch (BOE). By optimizing the time in ultrasonic bath and in BOE, the SiO₂ and the metal on top were removed completely which resulted in the gate metal only on the sidewalls. Both dry and wet etch techniques were investigated to reduce the gate leakage on the etched surface. The low power dry etch combined with the tetramethylammonium hydroxide wet etch can effectively reduce the etch damages, decrease the gate leakage and enhance the gate control over the channel.

Abstracts:We have validated that the electrical performances of the In_0.53Ga_0.47As MOSFETs such as sub-threshold slope (SS) and electron mobility were dependent on interfacial reactions in the metal/high- ${k}$ /InGaAs gate stacks which could be controlled remotely by choice of the metal electrodes. We demonstrated In_0.53Ga_0.47As MOSFETs with high mobility (peak mobility ~1300 cm²/Vs) and superior SS performance (SS 76.4 mV/dec) at the scaled CET region owing to the remote reduction of the native III–V oxide by the TiN electrodes.

Abstracts:Theoretical performance projections of a reconfigurable tunnel (RT) field-effect transistor (FET) employing multiple parallel 1-D channels are given. The RT-nanoFET can be reconfigured on demand from p- to n-type and from low power (LP) to high performance (HP) operation. In LP mode, a subthreshold swing $S$ below 60 mV/dec is predicted for a current density per gate width up to 3 nA/ $mu text{m}$ . By changing the polarities of the program gates to HP mode the current density can be increased to more than 110 $mu text{A}/mu text{m}$ . Thus, LP/HP reconfigurability liberates the transistor from the necessity to deliver low $S$ up to very high current densities.